Many integrated circuits (such as application specific integrated circuits, also called ASIC) include an embedded dynamic random access memory (eDRAM) block (also referred to as an eDRAM macro). By embedding the DRAM on the integrated circuit (IC) chip with a digital signal processor (DSP) or other special purpose hardware, the chip designer avoids large latency between the DSP or hardware and a separate memory chip. Compared to using a separate DRAM chip, eDRAM offers increased data bandwidth and reduced power consumption. The use of dDRAM also permits reduction in the overall footprint of products. Thus, eDRAM is increasingly popular in a large variety of electronic devices, including but not limited to cellular phones, smart phones, MP3 players, and portable laptops.
The ASIC environment in which the eDRAM is included may have a variety of system buses, and a variety of bus bandwidths. In designing a product, the IC designer will seek to match the bandwidth of the eDRAM (the number of input output pins, or I/Os) to the bandwidth of the system bus. One approach to generate different product configurations with different eDRAM macro bandwidths is a software solution using a compiler. However, this usually entails providing multiple eDRAM configurations corresponding to the different desired bandwidths and, therefore, has a high cost.
Another method to vary the number of I/Os for an eDRAM macro is to include a plurality of macros by abutment. For example, to double the bandwidth of a given macro, two memory macros may be included, instead of one. This approach grows the physical size of the memory when a wider data bus is required. This doubles the area devoted to the eDRAM macro.